Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (Hardcover)

Name: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Author: Krishnendu Chakrabarty, Brandon Noia

von Krishnendu Chakrabarty, Brandon Noia Verlag: Springer International Publishing

2014 - Erschienen 02.12.2013 - Gebunden, 264 Seiten, 241mm x 160mm x 20mm, Sprache(n): eng

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Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICsIncludes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizationsEncompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

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MARZIES Buch- und Medienhandel

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A21976544

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ISBN:

3319023772

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