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Kundu, Sudipta; Lerner, Sorin; Gupta, Rajesh K.

High-Level Verification Methods and Tools for Verification of System-Level Designs (Gebundene Ausgabe)

Springer-Verlag GmbH, Springer US, New York, N.Y., Mai 2011


167 S. - Sprache: Englisch - 31 schwarz-weiße Abbildungen, 6 schwarz-weiße Tabellen - 245x164x18 mm Book

ISBN: 1441993584 EAN: 9781441993588

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.


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Produktdetails

Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification Uses a combination of formal techniques to do scalable verification of system designs completely automatically Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL Written by researchers in work in mainstream hardware and software design and includes results from both academia and industry

Inhaltsverzeichnis

Introduction.- Related Work.- Background.- Execution-based Model Checking for High-Level Designs.- Efficient Symbolic Analysis for Concurrent Programs.- Translation Validation of High-Level Synthesis.- Parameterized Program Equivalence Checking.- Conclusions and Future Work.


ISBN 1-441993-58-4, ISBN 1-44-199358-4, ISBN 1-44199-358-4, ISBN 1-441-99358-4, ISBN 1-4419-9358-4

ISBN 978-1-441993-58-8, ISBN 978-1-44-199358-8, ISBN 978-1-44199-358-8, ISBN 978-1-441-99358-8, ISBN 978-1-4419-9358-8

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