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Gogniat, Guy (Herausgeber); Milojevic, Dragomir (Herausgeber); Morawiec, Adam (Herausgeber); Erdogan, Ahmet (Herausgeber)

Algorithm-Architecture Matching for Signal and Image Processing Best papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009 (Gebundene Ausgabe)

Reihe: Lecture Notes in Electrical Engineering 73

Springer-Verlag GmbH, Springer Netherland, Juli 2011

296 S. - Sprache: Englisch - 241x162x25 mm

ISBN: 9048199646 EAN: 9789048199648

Advances in signal and image processing together with increasing computing power are bringing mobile technology closer to applications in a variety of domains like automotive, health, telecommunication, multimedia, entertainment and many others. The development of these leading applications, involving a large diversity of algorithms (e.g. signal, image, video, 3D, communication, cryptography) is classically divided into three consecutive steps: a theoretical study of the algorithms, a study of the target architecture, and finally the implementation. Such a linear design flow is reaching its limits due to intense pressure on design cycle and strict performance constraints. The approach, called Algorithm-Architecture Matching, aims to leverage design flows with a simultaneous study of both algorithmic and architectural issues, taking into account multiple design constraints, as well as algorithm and architecture optimizations, that couldn't be achieved otherwise if considered separately. Introducing new design methodologies is mandatory when facing the new emerging applications as for example advanced mobile communication or graphics using sub-micron manufacturing technologies or 3D-Integrated Circuits. This diversity forms a driving force for the future evolutions of embedded system designs methodologies.The main expectations from system designers' point of view are related to methods, tools and architectures supporting application complexity and design cycle reduction. Advanced optimizations are essential to meet design constraints and to enable a wide acceptance of these new technologies.Algorithm-Architecture Matching for Signal and Image Processing presents a collection of selected contributions from both industry and academia, addressing different aspects of Algorithm-Architecture Matching approach ranging from sensors to architectures design. The scope of this book reflects the diversity of potential algorithms, including signal, communication, image, video, 3D-Graphics implemented onto various architectures from FPGA to multiprocessor systems. Several synthesis and resource management techniques leveraging design optimizations are also described and applied to numerous algorithms.Algorithm-Architecture Matching for Signal and Image Processing should be on each designer's and EDA tool developer's shelf, as well as on those with an interest in digital system design optimizations dealing with advanced algorithms.

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Provides last optimization techniques for implementing signal and image processing Highlights advanced techniques for dynamic and partial reconfigurable systems Introduces next generation CAD tools for signal and image processing Present emerging RTOS and scheduling techniques for embedded systems


Preface. Part 1: Architectures for embedded applications. Chapter 1: Architectures for image processing. Lossless Multi-mode Interband Image Compression and its Hardware Architecture. Efficient Memory Management for Uniform and Recursive Grid Traversal. Chapter 2: Architectures for signal and telecommunication processing. Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. Part 2: Data acquisition and embedded systems. Chapter 3: Sensors for data acquisition. A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimization. Chapter 4: Operators for embedded systems. Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. Chapter 5: Partial and dynamic reconfiguration for signal and image processing. RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip. A New three-Level Strategy for Off-line Placement of Hardware Tasks on Partially and Dynamically Reconfigurable Hardware. End-to-end Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. Part 3: Embedded systems design. Chapter 6: RTOS for embedded systems. SystemC multiprocessor RTOS model for services distribution on MPSoC platforms. Chapter 7: Scheduling of embedded systems. A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention. Multiprocessor scheduling of dataflow programs within the Reconfigurable Video Coding framework. Chapter 8: CAD tools for signal and image processing. A High Level Synthesis Flow Using Model Driven Engineering. Generation of Hardware/Software systems based on CAL dataflow description.

ISBN 9-048199-64-6, ISBN 9-04-819964-6, ISBN 9-04819-964-6, ISBN 9-048-19964-6, ISBN 9-0481-9964-6

ISBN 978-9-048199-64-8, ISBN 978-9-04-819964-8, ISBN 978-9-04819-964-8, ISBN 978-9-048-19964-8, ISBN 978-9-0481-9964-8

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